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Equipped with ARM ® architecture ® - M7 kernel STM32F7 series high performance MCU

  • Category:ST

  • Hit Count:35
  • Date:2018-12-03
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Detailed introduction

Benefited from stmicroelectronics ART Accelerator ™ Accelerator and first-level CACHE [L1 CACHE], both from the internal flash memory and external memory executable program, STM32F7 microcontroller can release the highest performance theoretical value in M7 kernel architecture: in 216 MHz fCPU frequency, achieve 1082 CoreMark / 462 DMIPS performance test.



Smart system architecture with more new peripherals



STM32F7 series fully release the full potential of cortex-m7 kernel:



• AXI and multi-ahb bus matrices interconnect processor cores, peripheral interfaces, and memory at high speeds


• up to 16 KB +16 KB instruction and data cache combinations


• up to 2mb built-in flash memory, some product models provide the function of reading and writing at the same time


• 2 general DMA controllers, Ethernet dedicated DMA controllers (some product models), high-speed USB on-the-go interface and chrom-art graphics accelerator (some product models)


• dual clock system makes peripheral clock independent from CPU clock, and the change of system clock does not affect the running of peripheral


• more peripheral interfaces, for example, 2 serial audio interfaces (SAI) supporting SPDIF output, 3 I squared S semi-duplex interfaces supporting SPDIF input, 2 USB OTG interfaces with built-in dedicated power supply, and dual-mode quad-spi flash memory interfaces


• distributed architecture large capacity SRAM memory:


- up to 512 KB universal data storage, including up to 128 KB of tightly coupled data storage (DTCM) for time-sensitive data processing (e.g., stack and heap... )


- 16 KB tightly coupled instruction memory (ITCM) for time sensitive program execution


-4 KB backup SRAM for saving data in the lowest power consumption mode


• some product models support program operation safety protection function (pc-rop)


• some product models support the integration of high-speed USB PHY on the chip



The energy efficiency



• at 1.8v, 7 CoreMark/mW


• in the stop mode, the typical working current is 100 A, and all registers and SRAM contents can be maintained



compatibility



• cortex-m7 downward compatible with the cortex-m4 instruction set


• STM32F7 series is compatible with STM32F4 series pin to pin *



* [note] : please refer to the data manual for the specific compatibility of 64 pins and 100 pins


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